Encoding method and device, decoding method and device, and storage medium

ABSTRACT

Provided are an encoding method and device, a decoding method and device, and a storage medium. The encoding method comprises: encoding an initial to-be-encoded bit sequence with a low density parity check code LDPC having a code rate R1, to obtain an encoded first bit sequence, where 0≤R1≤1; linearly combining at least two bit sequence segments in the first bit sequence to obtain a second bit sequence; and cascading the first bit sequence and the second bit sequence to obtain a target bit sequence having a code rate R2, where 0≤R2≤R1≤1.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims priority to PCT ApplicationNo. PCT/CN2017/095474 filed Aug. 1, 2017, which is based upon and claimspriority to Chinese Patent Application No. 201610668564.1, filed Aug.12, 2016, the entire contents of which are incorporated herein byreference.

TECHNICAL FIELD

The present disclosure relates to the field of communication, and moreparticularly to an encoding method and device, a decoding method anddevice, and a storage medium.

BACKGROUND

The transmitting end of the digital communication system usuallyincludes a source, a channel encoder and a modulator, and the receivingend usually includes a demodulator, a channel decoder and a destination,as shown in FIG. 1. The channel encoder is configured to introduceredundant information into original information according to a certainrule, so that the channel decoder at the receiving end can correct tosome extent the errors occurring when the information is transmitted onthe channel.

Low Density Parity Check Code (LDPC) is a linear block code based on asparse check matrix, which utilizes the sparsity of its check matrix toachieve encoding and decoding of low complexity. This makes the LDPCcode practical.

The graphical representation of the LDPC parity check matrix is abipartite graph. There is a one-to-one correspondence between thebipartite graph and the check matrix. One M*N parity check matrix Hdefines a constraint that each codeword having N bits satisfies M paritychecks. One bipartite graph includes N variable nodes and M parity checknodes. When the m-th check involves the n-th bit, that is, the elementH_(m) of the m-th row and the n-th column in H, n=1, there will be aedge between the check node m and the variable node n. In the bipartitegraph, there is no connection between any variable nodes or between anycheck nodes, and the total number of edges in the bipartite graph isequal to the number of non-zero elements in the check matrix.

A special type of LDPC code has become a major application due to itsstructured features. For example, a LDPC parity check matrix H with sizeof (M×z)×(N×z) is composed of M×N block matrices. Each block matrix is adifferent power of a z×z basic permutation matrix. where the basicpermutation matrices are all cyclic shift matrices of the unit matrix(right shift in default herein) with following form:

$H = {\begin{bmatrix}P^{h_{00}^{b}} & P^{h_{01}^{b}} & P^{h_{02}^{b}} & \ldots & P^{h_{0n_{b}}^{b}} \\P^{h_{10}^{b}} & P^{h_{11}^{b}} & P^{h_{l2}^{b}} & \ldots & P^{h_{1n_{b}}^{b}} \\\ldots & \ldots & \ldots & \ldots & \ldots \\P^{h_{m_{b}0}^{b}} & P^{h_{m_{b}1}^{b}} & P^{h_{m_{b}2}^{b}} & \ldots & P^{h_{m_{b}n_{b}}^{b}}\end{bmatrix} = P^{H_{b}}}$

If h_(ij) ^(b)=−1, then P^(h) ^(ij) ^(b) =0

If h_(ij) ^(b) is an integer greater than or equal to 0, define P^(h)^(ij) ^(b) =(P)^(h) ^(ij) ^(b) , where P is a z×z standard permutationmatrix, as follows:

$P = \begin{bmatrix}0 & 1 & 0 & \ldots & 0 \\0 & 0 & 1 & \ldots & 0 \\\ldots & \ldots & \ldots & \ldots & \ldots \\0 & 0 & 0 & \ldots & 1 \\1 & 0 & 0 & \ldots & 0\end{bmatrix}$

Each of these block matrices can be uniquely identified by such a powerh_(ij) ^(b). If the matrix is zero matrix, the h_(ij) ^(b) is usuallyrepresented by −1. Thus, if each block matrix of H is replaced by itspower, a M×N matrix H_(b) is obtained. Here, it is defined that H_(b) isthe basic matrix of H, and H is referred to as the extension matrix ofH_(b). In actual encoding, z=code length/number N of columns of the basematrix, which is referred to as a lifting factor.

For example, a matrix is as follows:

$H = \begin{bmatrix}1 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 \\0 & 1 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 0 \\0 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\0 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 1 & 0 \\1 & 0 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 1 \\0 & 1 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 0\end{bmatrix}$

It can be extended with the following parameter z and a 2×4 base matrixH_(b):

$z = {{3\mspace{14mu}{and}\mspace{14mu} H_{b}} = \begin{bmatrix}0 & 1 & 0 & {- 1} \\2 & 1 & 2 & 1\end{bmatrix}}$

Therefore, it can also be said that the encoder of such an LDPC code isuniquely generated by the base matrix H_(b), the spreading factor z andthe selected basic permutation matrix.

The code rate of the LDPC code is related to the size of the paritycheck matrix or the base matrix. For example, the LDPC code ratecorresponding to a base matrix of M rows and N columns is R=(N−M)/N.

For example, a matrix 1

$\begin{matrix}0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & {- 1} & {- 1} & {- 1} \\464 & 63 & 153 & 53 & 476 & 176 & 18 & 243 & 430 & 0 & {- 1} & {- 1} \\167 & 26 & 131 & 438 & 345 & 498 & 251 & 371 & {- 1} & 280 & 0 & {- 1} \\128 & 363 & 443 & 285 & 316 & 69 & 473 & 22 & {- 1} & {- 1} & 455 & 0\end{matrix}$

is a basic matrix of 4 rows and 12 columns, the code rate of the LDPCcode corresponding to the matrix is 2/3;

a matrix 2

$\begin{matrix}0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} \\232 & 31 & 76 & 26 & 238 & 88 & 9 & 121 & 215 & 0 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} \\83 & 13 & 65 & 219 & 172 & 249 & 125 & 185 & {- 1} & 140 & 0 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} \\64 & 181 & 221 & 142 & 157 & 34 & 236 & 11 & {- 1} & {- 1} & 227 & 0 & {- 1} & {- 1} & {- 1} & {- 1} \\227 & 77 & 232 & {- 1} & 10 & {- 1} & 99 & {- 1} & {- 1} & {- 1} & {- 1} & 136 & 0 & {- 1} & {- 1} & {- 1} \\70 & 219 & 104 & {- 1} & {- 1} & 91 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & 0 & {- 1} & {- 1} \\7 & 165 & {- 1} & 110 & {- 1} & 203 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & 0 & {- 1} \\109 & 161 & {- 1} & 193 & 7 & {- 1} & 64 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & 0\end{matrix}$

is a basic matrix of 8 rows and 16 columns, the code rate of the LDPCcode corresponding to the matrix is 1/2;

a matrix 3

$\begin{matrix} & & & & & & & & & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} \\928 & 126 & 306 & 106 & 952 & 352 & 36 & 486 & 860 & 0 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} \\335 & 52 & 262 & 876 & 690 & 996 & 502 & 742 & {- 1} & 561 & 0 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} \\256 & 726 & 886 & 570 & 630 & 138 & 946 & 44 & {- 1} & {- 1} & 911 & 0 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} \\910 & 310 & 928 & {- 1} & 40 & {- 1} & 396 & {- 1} & {- 1} & {- 1} & {- 1} & 544 & 0 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} \\280 & 876 & 418 & {- 1} & {- 1} & 365 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & 0 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} \\28 & 660 & {- 1} & 442 & {- 1} & 814 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & 0 & {- 1} & {- 1} & {- 1} & {- 1} \\438 & 646 & {- 1} & 772 & 30 & {- 1} & 257 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & 0 & {- 1} & {- 1} & {- 1} \\420 & 768 & {- 1} & {- 1} & {- 1} & 330 & {- 1} & {- 1} & 609 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & 0 & {- 1} & {- 1} \\136 & 936 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & 71 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & 0 & {- 1} \\148 & 40 & 382 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & 284 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & 0 \\486 & 928 & {- 1} & 399 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} \\781 & 400 & {- 1} & {- 1} & 618 & {- 1} & 296 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} \\290 & 606 & {- 1} & {- 1} & {- 1} & 418 & {- 1} & 748 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} \\502 & 420 & {- 1} & {- 1} & {- 1} & {- 1} & 705 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} \\756 & 100 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & 977 & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1} & {- 1}\end{matrix}\begin{matrix}{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\0 \\{- 1} \\{- 1} \\{- 1} \\{- 1}\end{matrix}\begin{matrix}{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\0 \\{- 1} \\{- 1} \\{- 1}\end{matrix}\begin{matrix}{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\0 \\{- 1} \\{- 1}\end{matrix}\begin{matrix}{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\0 \\{- 1}\end{matrix}\begin{matrix}{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\{- 1} \\0\end{matrix}$

is a basic matrix of 16 rows and 24 columns, and the code rate of theLDPC code corresponding to the matrix is 1/3. It can be seen that theparity check matrix or base matrix of a low code rate LDPC code usuallyrequires a larger number M of rows.

There are many decoding algorithms for LDPC codes. Among them, MessagePassing algorithm or Belief Propagation algorithm (BP algorithm) are themainstream and basic algorithms of LDPC codes. At present, there aremany improved effective decoding algorithms. A decoding algorithmfrequently used by industry is Layered Belief Propagation algorithm(Layered-BP algorithm). The Layered-BP algorithm has the advantages ofless iterations and faster convergence. However, the hardware delay ofthe decoder based on the Layered-BP algorithm is related to the coderate of the parity check matrix or the base matrix. The lower the coderate is, the more rows of the matrix requires, the smaller theparallelism is, the larger delay is and the lower throughput is. Thereis also a typical decoding algorithm called full parallel decodingalgorithm. The full parallel decoding algorithm has the advantages ofhigh parallelism, small delay and high throughput, but the complexity ofthe decoder hardware based on the full parallel algorithm is alsorelated to the code rate of the parity check matrix or the base matrix.The lower the code rate is, the larger the matrix is, the higherhardware complexity is, and the more difficult the hardwareimplementation is.

As can be seen from the above description, although increasing thenumber of rows of the parity check matrix or the basic matrix of theLDPC code can obtain a lower encoding rate, this will also increase thedecoding delay or complexity of the decoder.

At present, there is no feasible solution at present for the problem inthe related art that low code rate LDPC encoding will increase thedecoding delay and hardware complexity of the decoder.

SUMMARY

The embodiments of the present disclosure provide an encoding method anddevice, a decoding method and device, and a storage medium, so as to atleast solve the problem in the related art that code rate LDPC encodingwill increase the decoding delay and hardware complexity of the decoder.

According to an embodiment of the present disclosure, an encoding methodis provided, including:

encoding an initial bit sequence to be encoded with a low density paritycheck code LDPC having a code rate R₁, to obtain an encoded first bitsequence, where 0≤R₁≤1;

linearly combining at least two bit sequence segments in the first bitsequence to obtain a second bit sequence; and

cascading the first bit sequence and the second bit sequence to obtain atarget bit sequence having a code rate R₂, where 0≤R₂≤R₁≤1.

Optionally, before linearly combining at least two bit sequence segmentsin the first bit sequence to obtain a second bit sequence, the methodfurther includes:

dividing the first bit sequence into t bit sequence segments, where arelationship exists between the number t of the bit sequence segmentsand the code rate R₁:

${t = {〚\frac{j}{R_{1}}〛}},$

where t is a positive integer greater than or equal to 1, j is apositive integer, and the operator

represents a rounding operation.

Optionally, linearly combining at least two bit sequence segments in thefirst bit sequence to obtain a second bit sequence includes:

a selecting step of selecting t₁ bit sequence segments from t bitsequence segments;

a determining step of linearly combining bits at corresponding positionsin the t₁ bit sequence segments to obtain a bit sequence segment D₁,where 1<t₁≤t;

repeating the selecting step and the determining step to generate w bitsequence segments {D₁, D₂, . . . , D_(w)}, where w is a positiveinteger; and

a cascading step of cascading the w bit sequence segments to obtain thesecond bit sequence.

Optionally, linearly combining bits at corresponding positions in the t₁bit sequence segments includes at least one of:

performing binary addition of the bits at corresponding positions in thet₁ bit sequence segments; and

first performing interleaving on at least two bit sequence segments ofthe t₁ bit sequence segments, and then performing binary addition of thebits at corresponding positions in the t₁ bit sequence segments.

Optionally, selecting t₁ bit sequence segments from t bit sequencesegments includes at least one of:

performing selection according to a pre-determined rule between anencoding end and a decoding end;

performing selection according to an indication in a signal sent fromthe encoding end to the decoding end; and

performing selection according to an indication in a signal sent fromthe decoding end to the encoding end.

Optionally, the number w of bit sequence segments is determinedaccording to t, R₁, and R₂.

Optionally, the number w of bit sequence segments of the second bitsequence is determined according to a formula of:

${w = {〚{t \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)}〛}},$

where, the operator

represents a rounding operation.

Optionally, a bit length L₂ of the second bit sequence is determinedaccording to L₁, R₁, and R₂, wherein L₁ is a bit length of the first bitsequence.

Optionally, the bit length L₂ of the second bit sequence is determinedaccording to a formula of:

${L_{2} = {〚{L_{1} \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)}〛}},$

where, the operator

represents a rounding operation.

Optionally, when R₁=1/3, R₂=1/5, and the first bit sequence includes 3bit sequence segments {P1, P2, P3}, the method further includes:

linearly combining the bit sequence segments P1 and P2, and linearlycombining the bit sequence segments P1 and P3 to obtain a second bitsequence; and

cascading the first bit sequence and the second bit sequence to obtain atarget bit sequence having a code rate R₂=1/5.

According to another aspect of the present disclosure, a decoding methodis provided, including: decoding a target bit sequence of code rate R₂with a low density parity check code LDPC of code rate R₁, to obtain aninitial bit sequence to be encoded, where 0≤R₂≤R₁≤1, wherein the targetbit sequence is formed by cascading a first bit sequence and a secondbit sequence, the first bit sequence is obtained by encoding an initialbit sequence to be encoded with a LDPC having a code rate R₁, and thesecond bit sequence is obtained by linearly combining at least two bitsequence segments in the first bit sequence.

According to another embodiment of the present disclosure, an encodingdevice is provided, including:

a first encoding module configured to encode an initial bit sequence tobe encoded with a low density parity check code LDPC having a code rateR₁, to obtain an encoded first bit sequence, where 0≤R₁≤1;

a second encoding module configured to linearly combine at least two bitsequence segments in the first bit sequence to obtain a second bitsequence; and

a third encoding module configured to cascade the first bit sequence andthe second bit sequence to obtain a target bit sequence having a coderate R₂, where 0≤R₂≤R₁≤1.

Optionally, the second encoding module is further configured to

divide the first bit sequence into t bit sequence segments, where arelationship exists between the number t of the bit sequence segmentsand the code rate R₁:

${t = {〚\frac{j}{R_{1}}〛}},$

where t is a positive integer greater than or equal to 1, j is apositive integer, and the operator

represents a rounding operation.

Optionally, the second encoding module includes:

a selection unit configured to select t₁ bit sequence segments from tbit sequence segments of the first bit sequence;

a combining unit configured to linearly combine bits at correspondingpositions in the t₁ bit sequence segments to obtain a bit sequencesegment D₁, where 1<t₁≤t; and

a cascading unit configured to cascade the w bit sequence segments {D₁,D₂, . . . , D_(w)} generated by the selection unit and the combiningunit to obtain the second bit sequence, where w is a positive integer.

Optionally, the combining unit is further configured to perform at leastone of:

performing binary addition of the bits at corresponding positions in thet₁ bit sequence segments; and

first performing interleaving on at least two bit sequence segments ofthe t₁ bit sequence segments, and then performing binary addition of thebits at corresponding positions in the t₁ bit sequence segments.

Optionally, the combining unit is further configured to:

according to a pre-determined rule between an encoding end and adecoding end, select t₁ bit sequence segments from t bit sequencesegments;

according to an indication in a signal sent from the encoding end to thedecoding end, select t₁ bit sequence segments from t bit sequencesegments; and

according to an indication in a signal sent from the decoding end to theencoding end, select t₁ bit sequence segments from t bit sequencesegments.

Optionally, the number w of bit sequence segments of the second bitsequence is determined according to t, R₁, and R₂.

Optionally, the number w of bit sequence segments of the second bitsequence is determined according to a formula of:

${w = {〚{t \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)}〛}},$

where, the operator

represents a rounding operation.

Optionally, a bit length L₂ of the second bit sequence is determinedaccording to L₁, R₁, and R₂, wherein L₁ is a bit length of the first bitsequence.

Optionally, the bit length L₂ of the second bit sequence is determinedaccording to a formula of:

${L_{2} = {〚{L_{1} \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)}〛}},$

where, the operator

represents a rounding operation.

Optionally, when R₁=1/3, R₂=1/5, and the first bit sequence includes 3bit sequence segments {P1, P2, P3},

the combining unit is further configured to linearly combine the bitsequence segments P1 and P2, and linearly combine the bit sequencesegments P1 and P3 to obtain a second bit sequence; and

the cascading unit is further configured to cascade the first bitsequence and the second bit sequence to obtain a target bit sequencehaving a code rate R₂=1/5.

According to another embodiment of the present disclosure, a decodingdevice is provided, including:

a decoding module configured to decode a target bit sequence having acode rate R₂ with a low density parity check code LDPC having a coderate R₁, where 0≤R₂≤R₁≤1,

wherein the target bit sequence is formed by cascading a first bitsequence and a second bit sequence,

the first bit sequence is obtained by encoding an initial bit sequenceto be encoded with a LDPC having a code rate R₁,

and the second bit sequence is obtained by linearly combining at leasttwo bit sequence segments in the first bit sequence.

According to another embodiment of the present disclosure, an encodingdevice is provided, including a first processor and a first memoryconfigured to store instructions executable by the first processor,wherein when the instructions are executed by the first processor, thefirst processor is configured to perform:

encoding an initial bit sequence to be encoded with a low density paritycheck code LDPC having a code rate R₁, to obtain an encoded first bitsequence, where 0≤R₁≤1;

linearly combining at least two bit sequence segments in the first bitsequence to obtain a second bit sequence; and

cascading the first bit sequence and the second bit sequence to obtain atarget bit sequence having a code rate R₂, where 0≤R₂<R₁<1.

Optionally, before linearly combining at least two bit sequence segmentsin the first bit sequence to obtain a second bit sequence, the firstprocessor is further configured to perform:

dividing the first bit sequence into t bit sequence segments, where arelationship exists between the number t of the bit sequence segmentsand the code rate R₁:

${t = {〚\frac{j}{R_{1}}〛}},$

where t is a positive integer greater than or equal to 1, j is apositive integer, and the operator

represents a rounding operation.

Optionally, the first processor is further configured to perform:

a selecting step of selecting t₁ bit sequence segments from t bitsequence segments;

a combining step of linearly combining bits at corresponding positionsin the t₁ bit sequence segments to obtain a bit sequence segment D₁,where 1<t₁≤t;

repeating the selecting step and the combining step to generate w bitsequence segments {D₁, D₂, . . . , D_(w)}, where w is a positiveinteger; and

cascading the w bit sequence segments to obtain the second bit sequence.

Optionally, the first processor selecting t1 bit sequence segments fromt bit sequence segments of the first bit sequence includes an operationof at least one of:

performing selection according to a pre-determined rule between anencoding end and a decoding end;

performing selection according to an indication in a signal sent fromthe encoding end to the decoding end; and

performing selection according to an indication in a signal sent fromthe decoding end to the encoding end.

According to another embodiment of the present disclosure, a decodingdevice is provided, including a second processor and a second memoryconfigured to store instructions executable by the second processor,wherein when the instructions are executed by the second processor, thesecond processor is configured to perform operations of:

decoding a target bit sequence having a code rate R₂ with a low densityparity check code LDPC having a code rate R₁, to obtain an initial bitsequence to be encoded, where 0≤R₂≤R₁≤1, wherein the target bit sequenceis formed by cascading a first bit sequence and a second bit sequence,the first bit sequence is obtained by encoding an initial bit sequenceto be encoded with a LDPC having a code rate R₁, and the second bitsequence is obtained by linearly combining at least two bit sequencesegments in the first bit sequence.

According to another embodiment of the present disclosure, a storagemedium is provided. The computer storage medium may store executioninstructions for performing the implementation of the encoding method orthe decoding method in the above embodiments.

Through the embodiments of the present disclosure, the initial bitsequence is encoded with the LDPC of a low code rate R₁, to obtain afirst bit sequence, and the first bit sequence is segmented. Then, atleast two bit sequence segments in the first bit sequence are combinedlinearly to obtain a second bit sequence. The first bit sequence and thesecond bit sequence are cascaded to obtain a target bit sequence of alower code rate R₂, where 0≤R₂≤R₁≤1. In this way, during thetransmission of the target bit sequence, the code rate R₂ is lower, itcan ensure the propagation speed. In the decoding stage, since thetarget bit sequence is obtained by cascading the first bit sequence andthe second bit sequence, the decoder can directly decode with the LDPCof the code rate R₁. Therefore, the present disclosure can solve theproblem in the related art that low code rate LDPC encoding willincrease the decoding delay and hardware complexity of the decoder, andthe decoding delay and hardware complexity of the decoder won't beincreased while obtaining a LDPC encoding of a low code rate.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings described herein are intended to provide afurther understanding of the present disclosure, and are intended to bea part of the present disclosure. The illustrative embodiments of thepresent disclosure and the description thereof are for explaining thepresent disclosure and do not constitute an undue limitation of thepresent invention. In the drawings:

FIG. 1 is a topological diagram of a transmitting end and a receivingend of a communication system in the related art;

FIG. 2 is a flowchart of an encoding method according to a firstembodiment of the present disclosure;

FIG. 3 is a flowchart of a decoding method according to the firstembodiment of the present disclosure;

FIG. 4 is a first block diagram showing the structure of an encodingdevice according to a second embodiment of the present disclosure;

FIG. 5 is a second block diagram showing the structure of an encodingdevice according to the second embodiment of the present disclosure;

FIG. 6 is a block diagram showing the structure of a decoding deviceaccording to the second embodiment of the present disclosure;

FIG. 7 is a block diagram showing the structure of an encoding deviceaccording to a third embodiment of the present disclosure;

FIG. 8 is a block diagram showing the structure of a decoding deviceaccording to the third embodiment of the present disclosure;

FIG. 9 is a schematic diagram of an encoding method according to anexemplary embodiment 2 of the present disclosure;

FIG. 10 is a schematic diagram of an encoding method according to anexemplary embodiment 3 of the present disclosure; and

FIG. 11 is a schematic diagram of an encoding method according to anexemplary embodiment 4 of the present disclosure.

DETAILED DESCRIPTION

The present disclosure will be described in detail below with referenceto the drawings in conjunction with the embodiments. It should be notedthat the embodiments in the present application and the features in theembodiments may be combined with each other if these features orembodiment do not conflict with each other.

It is to be understood that the terms “first”, “second”, and the like inthe specification and claims of the present disclosure are used todistinguish similar objects, and are not necessarily used to describe aparticular order or sequence. It is to be understood that the numbersused in such way may be interchanged where appropriate, so that theembodiments of the present disclosure described herein can beimplemented in a sequence other than those illustrated or describedherein. In addition, the terms “include” and “have” and any variationsthereof are intended to cover non-exclusive inclusions. For example, aprocess, a method, a system, a product, or a device that includes aseries of steps or units is not necessarily limited to those steps orunits that are clearly listed, but may include other steps or units thatare not clearly listed or inherent to the process, the method, or thedevice.

First Embodiment

According to an embodiment of the present disclosure, an encoding methodembodiment is provided. It should be noted that the steps illustrated inthe flowchart of the figures may be performed in a computer system suchas a set of computer executable instructions. Although a logical orderis shown in the flowchart, but in some cases the steps shown ordescribed may be performed in a different order than the ones describedherein.

FIG. 2 is a flow chart of an encoding method according to the firstembodiment of the present disclosure. As shown in FIG. 2, thisembodiment provides an encoding method, including the following steps.

In S201, an initial bit sequence to be encoded is encoded with a lowdensity parity check code LDPC having a code rate R₁, to obtain anencoded first bit sequence, where 0≤R₁≤1.

In S203, at least two bit sequence segments in the first bit sequenceare combined linearly to obtain a second bit sequence.

In S205, the first bit sequence and the second bit sequence are cascadedto obtain a target bit sequence having a code rate R₂, where 0≤R₂≤R₁≤1.

Through the above steps, the initial bit sequence is encoded with theLDPC of a low code rate R₁, to obtain a first bit sequence, and thefirst bit sequence is segmented. Then, at least two bit sequencesegments in the first bit sequence are combined linearly to obtain asecond bit sequence. The first bit sequence and the second bit sequenceare cascaded to obtain a target bit sequence of a lower code rate R₂,where 0≤R₂≤R₁≤1. In this way, during the transmission of the target bitsequence, the code rate R₂ is lower, this can ensure the propagationspeed. In the decoding stage, since the target bit sequence is obtainedby cascading the first bit sequence and the second bit sequence, thedecoder can directly decode with the LDPC of the code rate R₁.Therefore, the embodiment can solve the problem in the related art thatlow code rate LDPC encoding will increase the decoding delay andhardware complexity of the decoder, and the decoding delay and hardwarecomplexity of the decoder won't be increased while obtaining a LDPCencoding of a low code rate.

In an exemplary solution of this embodiment, before at least two bitsequence segments in the first bit sequence are combined linearly toobtain a second bit sequence, the first bit sequence is first dividedinto t bit sequence segments, where there is a relationship between thenumber t of the bit sequence segments and the code rate R₁ as follows:

${t = {〚\frac{j}{R_{1}}〛}},$

where t is a positive integer greater than or equal to 1, j is apositive integer, and the operator

represents rounding up, rounding down, or rounding operation.

In another exemplary implementation of this embodiment, combininglinearly at least two bit sequence segments in the first bit sequence toobtain a second bit sequence specifically includes the following steps.

In a selecting step, t₁ bit sequence segments are selected from t bitsequence segments.

In a determining step: bits at corresponding positions are linearlycombined to the t₁ bit sequence segments to obtain a bit sequencesegment D₁, where 1<t₁≤t.

The above selecting step and determining step are repeated to generate wbit sequence segments {D₁, D₂, . . . , D_(w)}, where w is a positiveinteger.

In a cascading step: the w bit sequence segments are cascaded to obtainthe second bit sequence.

It should be noted that the linear combination of the bits at thecorresponding positions in the t₁ bit sequence segments in thedetermining step may be implemented by any of the following manners:

performing binary addition of the bits at corresponding positions in thet₁ bit sequence segments; or

first performing interleaving on at least two bit sequence segments ofthe t₁ bit sequence segments, and then performing binary addition of thebits at corresponding positions in the t₁ bit sequence segments.

However, the linear combination of the bits at the correspondingpositions in the bit sequence segment can be implemented by othermanners. Any equivalent substitution or extension on the basis of theembodiment is within the protection scope of the embodiment, which isnot limited in the embodiment.

In another exemplary solution of the present disclosure, how to selectt₁ bit sequence segments and which bit sequence segments are selectedfrom the t bit sequence segments of the first bit sequence arespecifically described, including but not limited to the followingmanners.

The selection may be performed according to a pre-determined rulebetween the encoding end and the decoding end, or may be performedaccording to an indication in a signal sent from the encoding end to thedecoding end, or may be performed according to an instruction in asignal sent from the decoding end to the encoding end.

The number w of bit sequence segments mentioned in the embodiment isdetermined according to t, R₁, and R₂. It may be determined according tothe following formula:

${w = {〚{t \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)}〛}},$

where, the operator

represents a rounding operation.

The bit length L₂ of the second bit sequence mentioned in thisembodiment is determined according to L₁, R₁, and R₂, and isspecifically determined according to the following formula:

${L_{2} = {〚{L_{1} \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)}〛}},$

where L₁ denotes the bit length of the first bit sequence, and theoperator

represents a rounding operation.

In an exemplary solution of the embodiment, a bit sequence O to bedecoded may be encoded with an LDPC code having a code rate of 1/3 toobtain an encoded bit sequence P. Then, the bit sequence P is dividedinto three bit sequence segments {P1, P2, P3}. After that, the bitsequence segments P1 and P2 are linearly combined, and the bit sequencesegments P1 and P3 are linearly combined to obtain a bit sequence Q; thebit sequence P and the bit sequence Q are cascaded to obtain a bitsequence S having a code rate of 1/5.

It can be seen from the above exemplary embodiment that during thetransmission of the bit sequence S, the code rate is 1/5, which canensure the propagation speed. In the decoding stage, since the bitsequence S is obtained by cascading the bit sequence P and the bitsequence Q, the decoder can directly decode the sequence with the LDPChaving a code rate of 1/3. Therefore, the embodiment can solve theproblem in the related art that low code rate LDPC encoding willincrease the decoding delay and hardware complexity of the decoder, andthus the decoding delay and hardware complexity of the decoder won't beincreased while obtaining a LDPC encoding of a low code rate.

It should be noted that the above encoding method may be performed by anencoder, or may be another device having an encoding function, which isnot limited in this embodiment.

In order to better understand the present disclosure, this embodimentalso provides a decoding method. FIG. 3 is a flowchart of a decodingmethod according to the first embodiment of the present disclosure. Asshown in FIG. 3, the decoding method includes the following steps.

In S301, a target bit sequence having a code rate R₂ is decoded with alow density parity check code LDPC having a code rate R₁, to obtain aninitial bit sequence to be encoded, where 0≤R₂≤R₁≤1.

The target bit sequence is formed by cascading a first bit sequence anda second bit sequence.

The first bit sequence is obtained by encoding an initial bit sequenceto be encoded with a LDPC having a code rate R₁.

The second bit sequence is obtained by linearly combining at least twobit sequence segments in the first bit sequence.

Through the above steps, a target bit sequence having a code rate R₂ isdecoded with a low density parity check code LDPC having a code rate R₁,where 0≤R₂≤R₁≤1, the target bit sequence is formed by cascading a firstbit sequence and a second bit sequence; the first bit sequence isobtained by encoding an initial bit sequence to be encoded with a LDPChaving a code rate R₁; and the second bit sequence is obtained bylinearly combining at least two bit sequence segments in the first bitsequence. Since the target bit sequence is obtained by cascading thefirst bit sequence and the second bit sequence, the decoder can directlydecode with the LDPC of the code rate R₁. Therefore, the presentembodiment can solve the problem in the related art that low code rateLDPC encoding will increase the decoding delay and hardware complexityof the decoder, and thus the present embodiment can achieve an effectthat the decoding delay and hardware complexity of the decoder won't beincreased while obtaining a LDPC encoding of a low code rate.

It should be noted that the above decoding method may be performed by andecoder, or may be another device having an decoding function, which isnot limited in this embodiment.

Through the description of the above embodiments, those skilled in theart can clearly understand that the methods according to the aboveembodiments can be implemented by means of software in combination witha necessary general hardware platform, and of course, can be implementedin hardware. But in many cases, the former is a better implementation.Based on such understanding, the technical solutions of the presentdisclosure, in essence or with a part contributing to the prior art, maybe embodied in the form of a software product stored in a storage medium(such as a ROM/RAM, a magnetic disk, an optical disc) includinginstructions for causing a terminal device (which may be a cell phone, acomputer, a server, or a network device, etc.) to perform the methods ofvarious embodiments of the present disclosure.

Second Embodiment

In this embodiment, an encoding device is provided, which is applied toan encoding apparatus, and is configured to implement the aboveembodiments and exemplary implementations. As used below, the term“module” may implement a combination of software and/or hardware of apredetermined function. Although the devices described in the followingembodiments are preferably implemented in software, hardware or acombination of software and hardware is also possible and can becontemplated.

FIG. 4 is a first block diagram showing the structure of an encodingdevice according to a second embodiment of the present disclosure. Asshown in FIG. 4, the encoding device includes the following modules.

A first encoding module 40 is configured to encode an initial bitsequence to be encoded with a low density parity check code LDPC havinga code rate R₁, to obtain an encoded first bit sequence, where 0≤R₁≤1.

A second encoding module 42 is connected to the first encoding module30, and is configured to linearly combine at least two bit sequencesegments in the first bit sequence to obtain a second bit sequence.

A third encoding module 44 is connected to the second encoding module32, and is configured to cascade the first bit sequence and the secondbit sequence to obtain a target bit sequence having a code rate R₂,where 0≤R₂≤R₁≤1.

Through the above encoding device, the first encoding module 40 encodesan initial bit sequence to be encoded with a low density parity checkcode LDPC having a code rate R₁, to obtain an encoded first bitsequence; the second encoding module 42 linearly combines at least twobit sequence segments in the first bit sequence to obtain a second bitsequence; the third encoding module 44 cascades the first bit sequenceand the second bit sequence to obtain a target bit sequence having acode rate R₂. The above technical solution can solve the problem in therelated art that low code rate LDPC encoding will increase the decodingdelay and hardware complexity of the decoder, and can thus achieve aneffect that the decoding delay and hardware complexity of the decoderwon't be increased while obtaining a LDPC encoding of a low code rate.

In an exemplary implementation of the embodiment, the second encodingmodule is further configured to divide the first bit sequence into t bitsequence segments, where there is a relationship between the number t ofthe bit sequence segments and the code rate R₁ as follows:

${t = {〚\frac{j}{R_{1}}〛}},$

where t is a positive integer greater than or equal to 1, j is apositive integer, and the operator

represents rounding up, rounding down, or rounding operation.

FIG. 5 is a second block diagram showing the structure of an encodingdevice according to the second embodiment of the present disclosure. Asshown in FIG. 5, in an exemplary implementation of the embodiment, thesecond encoding module 32 includes the following units.

A selection unit 420 is configured to select t₁ bit sequence segmentsfrom t bit sequence segments of the first bit sequence.

A combining unit 422 is configured to linearly combine bits atcorresponding positions in the t₁ bit sequence segments to obtain a bitsequence segment D₁, where 1<t₁≤t.

A cascading unit 424 is configured to cascade the w bit sequencesegments {D₁, D₂, . . . , D_(w)} generated by the selection unit and thecombining unit to obtain the second bit sequence, where w is a positiveinteger.

It should be noted that the linear combination of the bits at thecorresponding positions in the t₁ bit sequence segments in thedetermining step may be implemented by any of the following manners:

performing binary addition of the bits at corresponding positions in thet₁ bit sequence segments; or

first performing interleaving on at least two bit sequence segments ofthe t₁ bit sequence segments, and then performing binary addition of thebits at corresponding positions in the t₁ bit sequence segments.

However, the linear combination of the bits in the correspondingpositions in the bit sequence segment can be implemented by othermanners. Any equivalent substitution or extension on the basis of theembodiment is within the protection scope of the embodiment, which isnot limited in the embodiment.

In another exemplary embodiment of the present disclosure, how to selectt₁ bit sequence segments and which bit sequence segments are selectedfrom the t bit sequence segments of the first bit sequence arespecifically described, including but not limited to the followingmanners.

The selection may be performed according to a pre-determined rulebetween the encoding end and the decoding end, or may be performedaccording to an indication in a signal sent from the encoding end to thedecoding end, or may be performed according to an indication in a signalsent from the decoding end to the encoding end.

The number w of bit sequence segments mentioned in the embodiment isdetermined according to t, R₁, and R₂. It may be determined according tothe following formula:

${w = {〚{t \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)}〛}},$

where, the operator

represents a rounding operation.

The bit length L₂ of the second bit sequence mentioned in thisembodiment is determined according to L₁, R₁, and R₂, and isspecifically determined according to the following formula:

${L_{2} = {〚{L_{1} \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)}〛}},$

where L₁ denotes the bit length of the first bit sequence, and theoperator

represents a rounding operation.

In an exemplary implementation of the embodiment, an encoding device isalso provided, including the following modules.

A fourth encoding module is configured to encode a bit sequence O to bedecoded with an LDPC code having a code rate of 1/3 to obtain an encodedbit sequence P.

A dividing module is configured to divide the bit sequence P into threebit sequence segments {P1, P2, P3}.

A fifth encoding module is configured to linearly combine the bitsequence segments P1 and P2, and linearly combine the bit sequencesegments P1 and P3 to obtain a bit sequence Q.

A sixth encoding module is configured to cascade the bit sequence P andthe bit sequence Q to obtain a bit sequence S having a code rate of 1/5.

In order to better understand the present disclosure, this embodimentalso provides a decoding device. FIG. 6 is a block diagram showing thestructure of a decoding device according to the second embodiment of thepresent disclosure. As shown in FIG. 6, the decoding device 6 includesthe following modules.

A decoding module 60 is configured to decode a target bit sequencehaving a code rate R₂ with a low density parity check code LDPC having acode rate R₁, to obtain an initial bit sequence to be encoded, where0≤R₂≤R₁≤1,

wherein the target bit sequence is formed by cascading a first bitsequence and a second bit sequence;

the first bit sequence is obtained by encoding an initial bit sequenceto be encoded with a LDPC having a code rate R₁; and

the second bit sequence is obtained by linearly combining at least twobit sequence segments in the first bit sequence.

Through the above device, the decoding module decodes a target bitsequence having a code rate R₂ with a low density parity check code LDPChaving a code rate R₁, to obtain an initial bit sequence to be encoded,where the target bit sequence is formed by cascading a first bitsequence and a second bit sequence; the first bit sequence is obtainedby encoding an initial bit sequence to be encoded with a LDPC having acode rate R₁; and the second bit sequence is obtained by linearlycombining at least two bit sequence segments in the first bit sequence.The above technical solution can solve the problem in the related artthat low code rate LDPC encoding will increase the decoding delay andhardware complexity of the decoder, and can thus achieve an effect thatthe decoding delay and hardware complexity of the decoder won't beincreased while obtaining a LDPC encoding of a low code rate.

It should be noted that the entities to which the various modules andunits in the above embodiments of the present disclosure may be appliedto entities including at least an encoder or a decoder, and the abovemodules may be implemented in software or hardware. For the latter, thefollowing implementation may be, but not limited to: the above modulesare all located in the same processor (the processor is located in theabove encoder or decoder); or, the above modules are respectivelylocated in different processors in any combination.

Third Embodiment

In order to better understand the technical solutions of the aboveembodiments of the present disclosure, an embodiment of the presentdisclosure further provides a physical encoding device. FIG. 7 is ablock diagram showing the structure of an encoding device 7 according toa third embodiment of the present disclosure. As shown in FIG. 7, thephysical encoding device 7 includes a first processor 70 and a firstmemory 72 for storing instructions executable by the first processor 70,and when the instructions are executed by the first processor 70, thefollowing operations are performed:

encoding an initial bit sequence to be encoded with a low density paritycheck code LDPC having a code rate R₁, to obtain an encoded first bitsequence, where 0≤R₁≤1;

linearly combining at least two bit sequence segments in the first bitsequence to obtain a second bit sequence; and

cascading the first bit sequence and the second bit sequence to obtain atarget bit sequence having a code rate R₂, where 0≤R₂≤R₁≤1.

Through the encoding device, the first processor 70 encodes an initialbit sequence to be encoded with a low density parity check code LDPChaving a code rate R₁, to obtain an encoded first bit sequence, where0≤R₁≤1; combines at least two bit sequence segments in the first bitsequence linearly to obtain a second bit sequence; and cascades thefirst bit sequence and the second bit sequence to obtain a target bitsequence having a code rate R₂. The above technical solution can solvethe problem in the related art that low code rate LDPC encoding willincrease the decoding delay and hardware complexity of the decoder, andcan thus achieve an effect that the decoding delay and hardwarecomplexity of the decoder won't be increased while obtaining a LDPCencoding of a low code rate.

In an exemplary implementation of the embodiment of the presentdisclosure, before at least two bit sequence segments in the first bitsequence are combined linearly to obtain a second bit sequence, thefirst processor is further configured to perform:

dividing the first bit sequence into t bit sequence segments, wherethere is a relationship between the number t of the bit sequencesegments and the code rate R₁ as follows:

${t = {〚\frac{j}{R_{1}}〛}},$

where t is a positive integer greater than or equal to 1, j is apositive integer, and the operator

represents a rounding operation.

Preferably, the first processor is further configured to perform thefollowing operations:

a selecting step of selecting t₁ bit sequence segments from t bitsequence segments;

a combining step of: linearly combining bits at corresponding positionsin the t₁ bit sequence segments to obtain a bit sequence segment D₁,where 1<t₁≤t;

repeating the above selecting step and combining step to generate w bitsequence segments {D₁, D₂, . . . , D_(w)}, where w is a positiveinteger; and

cascading the w bit sequence segments to obtain the second bit sequence.

Preferably, linearly combining the bits at the corresponding positionsin the t₁ bit sequence segments includes at least one of the following:

performing binary addition of the bits at corresponding positions in thet₁ bit sequence segments; and

first performing interleaving on at least two bit sequence segments ofthe t₁ bit sequence segments, and then performing binary addition of thebits at corresponding positions in the t₁ bit sequence segments.

Preferably, the first processor selecting t1 bit sequence segments fromthe t bit sequence segments of the first bit sequence includes anoperation of at least one of the following:

performing selection according to a pre-determined rule between theencoding end and the decoding end;

performing selection according to an indication in a signal sent fromthe encoding end to the decoding end; and

performing selection according to an indication in a signal sent fromthe decoding end to the encoding end.

Preferably, the number w of the bit sequence segments is determinedaccording tot, R₁, R₂.

Preferably, the number w of bit sequence segments of the second bitsequence is determined according to the following formula:

${w = {〚{t \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)}〛}},$

where, the operator

represents a rounding operation.

Preferably, the bit length L₂ of the second bit sequence is determinedaccording to L₁, R₁, and R₂, where L₁ denotes the bit length of thefirst bit sequence.

Preferably, the bit length L₂ of the second bit sequence is determinedaccording to the following formula:

${L_{2} = {〚{L_{1} \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)}〛}},$

where, the operator

represents a rounding operation.

Preferably, when R₁=1/3, R₂=1/5, and the first bit sequence includesthree bit sequence segments {P1, P2, P3}, the method further includes:

linearly combining the bit sequence segments P1 and P2, and linearlycombining the bit sequence segments P1 and P3 to obtain a second bitsequence; and

cascading the first bit sequence and the second bit sequence to obtain atarget bit sequence having a code rate R₂=1/5.

In order to better understand the technical solution of the aboveembodiments of the present disclosure, an embodiment of the presentdisclosure further provides a physical decoding device. FIG. 8 is ablock diagram showing the structure of a decoding device according tothe third embodiment of the present disclosure. As shown in FIG. 8, thedecoding device 8 of this embodiment includes: a second processor 80 anda second memory 82 configured to store instructions executable by thesecond processor 80, and when the instructions are executed by thesecond processor 80, the following operations are performed:

decoding a target bit sequence having a code rate R₂ with a low densityparity check code LDPC having a code rate R₁, to obtain an initial bitsequence to be encoded, where 0≤R₂≤R₁≤1. The target bit sequence isformed by cascading a first bit sequence and a second bit sequence. Thefirst bit sequence is obtained by encoding an initial bit sequence to beencoded with a LDPC having a code rate R₁. The second bit sequence isobtained by linearly combining at least two bit sequence segments in thefirst bit sequence.

Through the above decoding device, the second processor 80 decodes atarget bit sequence having a code rate R₂ with a low density paritycheck code LDPC having a code rate R₁, to obtain an initial bit sequenceto be encoded, where 0≤R₂≤R₁≤1. The target bit sequence is formed bycascading a first bit sequence and a second bit sequence. The first bitsequence is obtained by encoding an initial bit sequence to be encodedwith a LDPC having a code rate R₁. The second bit sequence is obtainedby linearly combining at least two bit sequence segments in the firstbit sequence. The above technical solution can solve the problem in therelated art that low code rate LDPC encoding will increase the decodingdelay and hardware complexity of the decoder, and can thus achieve aneffect that the decoding delay and hardware complexity of the decoderwon't be increased while obtaining a LDPC encoding of a low code rate.

It should be noted that the physical encoding device and the physicaldecoding device may be a processing device such as a chip or a singlechip, or may be a physical device such as an encoder or a decoder, andembodiments of the present disclosure do not impose specific limitationson this.

For a better understanding of the present disclosure, some exemplaryembodiments are provided.

Exemplary Embodiment 1

In the embodiment of the present disclosure, an encoding method of a lowdensity parity check code is provided. The method includes the followingsteps.

In step 1, a first bit sequence I to be decoded (equivalent to theinitial bit sequence in the above embodiments) is encoded with a lowdensity parity check code having a code rate R₁ to obtain an encodedsecond bit sequence C (equivalent to the first bit sequence in the aboveembodiments), wherein 0≤R₁≤1.

In step 2, all or part of the bit sequence segments of the second bitsequence C are linearly combined to obtain a third bit sequence D(equivalent to the second bit sequence in the above embodiments).

In step 3, the second bit sequence C and the third bit sequence D arecascaded to form a fourth bit sequence E (corresponding to the targetbit sequence in the above embodiments) having a code rate R₂, where0≤R₂≤R₁≤1.

All or part of the bit sequence segments of the second bit sequence Cmeans that the second bit sequence C can be divided into t bit sequencesegments {C₁, C₂, . . . , C_(t)}, and there is a relationship betweenthe number t of the bit sequence segments and the code rate R₁ asfollows:

${t = {〚\frac{j}{R_{1}}〛}},$

where j is a positive integer, and the operator

represents a rounding operation such as rounding up, rounding down, andso on.

The method for linearly combining all or part of the bit sequences ofthe second bit sequence C to obtain the third bit sequence D includes:

selecting t₁ bit sequence segments from t bit sequence segments {C₁, C₂,. . . C_(t)} of the second bit sequence C, and linearly combining thebits at corresponding positions in the t₁ bit sequence segments toobtain a new bit sequence segment D₁, where t₁≤t; selecting t₂ bitsequence segments from t bit sequence segments {C₁, C₂, . . . C_(t)},and linearly combining the bits at corresponding positions in the t₂ bitsequence segments to obtain a new bit sequence segment D₂, where t₂≤t;and so on, until w new bit sequence segments {D₁, D₂, . . . , D_(w)} aregenerated. The w new bit sequence segments are cascaded to obtain athird bit sequence D.

Further, linearly combining the bits at corresponding positions in theplurality of bit sequence segments means performing binary addition(also referred to as “exclusive OR”) on the plurality of bits; orinterleaving part of the bit sequence segments, and then performingbinary addition (exclusive OR) on bits at the corresponding positions inthe plurality of bit sequence segments.

Further, the t_(i) (where 1≤i≤w) bit sequence segments for generating anew bit sequence segment D₁ may be pre-agreed between the transmittingend and the receiving end, or notified to the receiving end by thetransmitting end; or notified to the transmitting end by the receivingend.

Further, the number w of bit sequence segments of the third bit sequenceD can be determined by the target code rate R₂. Specifically,

${w = {〚{t \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)}〛}},$

where R₁ is the encoding rate of the second bit sequence C, t is thenumber of bit sequence segments of the second bit sequence C, and theoperator

represents a rounding operation such as rounding up, rounding down, andso on.

Further, the length L₂ (bit) of the third bit sequence D can bedetermined by the target code rate R₂. Specifically

${L_{2} = {〚{L_{1} \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)}〛}},$

where R₁ is the encoding rate of the second bit sequence C, L₁ is thelength (bit) of the second bit sequence C, and the operator

represents rounding up, rounding down, or rounding operation.

Exemplary Embodiment 2

FIG. 9 is a schematic diagram of an encoding method according to anexemplary embodiment 2 of the present disclosure. As shown in FIG. 9,for a low density parity check code having a code rate R₁, a low densityparity check code having a code rate R₂ can be obtained by the followingmethod. In this embodiment, it is assumed that R₁=1/3, R₂=1/5.

For a first bit sequence I to be decoded, assuming that the length ofthe first bit sequence I is 1000 bits, the first bit sequence I to bedecoded is encoded with a parity check matrix or a base matrix (forexample, basic check matrix of 16 rows and 24 columns) of a low densityparity check code having a code rate of R₁=1/3, to generate a second bitsequence C. The length of the second bit sequence C is L₁=3000 bits. Thesecond bit sequence C can be divided into a number t of bit sequencesegments:

$t = {{〚\frac{j}{R_{1}}〛} = 3}$

i.e., bit sequence segments {C₁, C₂, C₃}, where j has the value j=1. C₁is an information bit sequence segment, C₂ and C₃ are check bit sequencesegments. Each of the lengths of C₁, C₂, and C₃ is 1000 bits.

Part or all of the bit sequence segments in the second bit sequence Care linearly combined to obtain a third bit sequence D. The third bitsequence D includes a number w of bit sequence segments:

$w = {{〚{t \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)}〛} = 2}$

i.e., bit sequence segments {D₁, D₂}, each bit sequence segment having alength of 1000 bits. And the length of the third bit sequence D is 2000bits:

$L_{2} = {{〚{L_{1} \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)}〛} = 2000.}$

Specifically, t₁=2 bit sequence segments C₁ and C₂ are selected from t=3bit sequence segments {C₁, C₂, C₃} of the second bit sequence Caccording to a pre-agreed rule between the transmitting end and thereceiving end. C₁ is an information bit sequence segment, and C₂ is acheck bit sequence segment. Binary addition is performed on bits atcorresponding positions of the two bit sequence segments to obtain a newbit sequence segment D₁. t₂=2 bit sequence segments C₁ and C₃ areselected from t=3 bit sequence segments {C₁, C₂, C₃}, of which C₁ is aninformation bit sequence segment and C₃ is a check bit sequence segment.Binary addition is performed on bits at corresponding positions of thetwo bit sequence segments to obtain a new bit sequence segment D₂. Thenew bit sequences D₁ and D₂ are cascaded to obtain a third bit sequenceD={D₁, D₂}.

The second bit sequence C and the third bit sequence D are cascaded toobtain a fourth bit sequence E={C, D} having an encoding rate R₂=1/5.

Exemplary Embodiment 3

FIG. 10 is a schematic diagram of an encoding method according to anexemplary embodiment 3 of the present disclosure. As shown in FIG. 10,for a low density parity check code having a code rate R₁, a low densityparity check code having a code rate R₂ can be obtained by the followingmethod. In this embodiment, it is assumed that R₁=1/3, R₂=1/6.

For a first bit sequence I to be decoded, assuming that the length ofthe first bit sequence I is 1000 bits, the first bit sequence I to bedecoded is encoded with a parity check matrix or a base matrix (forexample, basic check matrix of 16 rows and 24 columns) of a low densityparity check code having a code rate of R₁=1/3, to generate a second bitsequence C. The length of the second bit sequence C is L₁=3000 bits. Thesecond bit sequence C can be divided into a number t of bit sequencesegments:

$t = {{〚\frac{j}{R_{1}}〛} = 3}$

i.e., bit sequence segments {C₁, C₂, C₃}, where j has the value j=1. C₁is an information bit sequence segment, C₂ and C₃ are check bit sequencesegments. Each of the lengths of C₁, C₂, and C₃ is 1000 bits.

Part or all of the bit sequence segments in the second bit sequence Care linearly combined to obtain a third bit sequence D. The third bitsequence D includes a number w of bit sequence segments:

$w = {{〚{t \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)}〛} = 3}$

i.e., bit sequence segments {D₁, D₂, D₃}, each bit sequence segmenthaving a length of 1000 bits. And the length of the third bit sequence Dis 3000 bits:

$L_{2} = {{〚{L_{1} \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)}〛} = 3000.}$

Specifically, t₁=2 bit sequence segments C₁ and C₂ are selected from t=3bit sequence segments {C₁, C₂, C₃} of the second bit sequence Caccording to a previously agreed rule between the transmitting end andthe receiving end. C₁ is an information bit sequence segment, and C₂ isa check bit sequence segment. The bit sequence segment C₂ of the 2 bitsequence segments is interleaved, and binary addition is performed onbits at corresponding positions of the two bit sequence segments(including interleaved bit sequence segment C₂ and un-interleaved bitsequence segment C₁) to obtain a new bit sequence segment D₁. t₂=2 bitsequence segments C₁ and C₃ are selected from t=3 bit sequence segments{C₁, C₂, C₃}, of which C₁ is an information bit sequence segment and C₃is a check bit sequence segment. Binary addition is performed on bits atcorresponding positions of the two bit sequence segments to obtain a newbit sequence segment D₂. t₃=3 bit sequence segments C₁, C₂, and C₃ areselected from t=3 bit sequence segments {C₁, C₂, C₃} of the second bitsequence C, of which C₁ is an information bit sequence segment, C₂ andC₃ are check bit sequence segments. The bit sequence segment C₃ of thethree bit sequence segments is interleaved, and binary addition isperformed on bits at corresponding positions of the three bit sequencesegments (including interleaved bit sequence segment C₃ andun-interleaved bit sequence segments C₁ and C₂) to obtain a new bitsequence segment D₃. The new bit sequences D₁, D₂ and D₃ are cascaded toobtain a third bit sequence D={D₁, D₂, D₃}.

The second bit sequence C and the third bit sequence D are cascaded toobtain a fourth bit sequence E={C, D} having an encoding rate R₂=1/6.

Exemplary Embodiment 4

FIG. 11 is a schematic diagram of an encoding method according to anexemplary embodiment 4 of the present disclosure. As shown in FIG. 11,for a low density parity check code having a code rate R₁, a low densityparity check code having a code rate R₂ can be obtained by the followingmethod. In this embodiment, it is assumed that R₁=2/3, R₂=1/3.

For a first bit sequence I to be decoded, assuming that the length ofthe first bit sequence I is 1000 bits, the first bit sequence I to bedecoded is encoded with a parity check matrix or a base matrix (forexample, basic check matrix of 4 rows and 12 columns) of a low densityparity check code having a code rate of R₁=2/3, to generate a second bitsequence C. The length of the second bit sequence C is L₁=1500 bits. Thesecond bit sequence C can be divided into a number t of bit sequencesegments:

$t = {{〚\frac{j}{R_{1}}〛} = 3}$

i.e., bit sequence segments {C₁, C₂, C₃}, where j has the value j=2. C₁and C₂ are information bit sequence segments, and C₃ is a check bitsequence segment. Each of the lengths of C₁, C₂, and C₃ is 500 bits.

Part or all of the bit sequence segments in the second bit sequence Care linearly combined to obtain a third bit sequence D. The third bitsequence D includes a number w of bit sequence segments:

$w = {{〚{t \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)}〛} = 3}$

i.e., bit sequence segments {D₁, D₂, D₃}, each bit sequence segmenthaving a length of 500 bits. And the length of the third bit sequence Dis 2000 bits:

$L_{2} = {{〚{L_{1} \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)}〛} = 2000.}$

Specifically, t₁=2 bit sequence segments C₁ and C₂ are selected fromt=−3 bit sequence segments {C₁, C₂, C₃} of the second bit sequence Caccording to a pre-agreed rule between the transmitting end and thereceiving end. C₁ is an information bit sequence segment, and C₂ is acheck bit sequence segment. Binary addition is performed on bits atcorresponding positions of the two bit sequence segments to obtain a newbit sequence segment D₁. t₂=2 bit sequence segments C₁ and C₃ areselected from t=3 bit sequence segments {C₁, C₂, C₃}, of which C₁ is aninformation bit sequence segment and C₃ is a check bit sequence segment.Binary addition is performed on bits at corresponding positions of thetwo bit sequence segments to obtain a new bit sequence segment D₂. t₃=2bit sequence segments C₂ and C₃ are selected from t=3 bit sequencesegments {C₁, C₂, C₃} of the second bit sequence C, of which C₂ and C₃are check bit sequence segments. The bit sequence segment C₃ of the twobit sequence segments is interleaved, and binary addition is performedon bits at corresponding positions of the two bit sequence segments(including interleaved bit sequence segment C₃ and un-interleaved bitsequence segment C₂) to obtain a new bit sequence segment D₃. The newbit sequences D₁, D₂ and D₃ are cascaded to obtain a third bit sequenceD={D₁, D₂, D₃}.

The second bit sequence C and the third bit sequence D are cascaded toobtain a fourth bit sequence E={C, D} having an encoding rate R₂=1/3.

Fourth Embodiment

An embodiment of the present disclosure also provides a storage medium.Optionally, in this embodiment, the storage medium may be configured tostore program codes executed as the encoding method and the decodingmethod provided in the first embodiment described above.

Optionally, in this embodiment, the storage medium may be located in anyone computer terminal of the computer terminal groups in the computernetwork, or in any one mobile terminal of the mobile terminal groups.

Optionally, in the embodiment, the storage medium is configured to storeprogram codes for performing the following steps:

S1, encoding an initial bit sequence to be encoded with a low densityparity check code LDPC having a code rate R₁, to obtain an encoded firstbit sequence, where 0≤R₁≤1;

S2, linearly combining at least two bit sequence segments in the firstbit sequence to obtain a second bit sequence; and

S3, cascading the first bit sequence and the second bit sequence toobtain a target bit sequence having a code rate R₂, where 0≤R₂≤R₁≤1.

An embodiment of the present disclosure also provides a storage medium.Optionally, in this embodiment, the storage medium may be configured tostore program codes for performing the following steps:

S1, decoding a target bit sequence having a code rate R₂ with a lowdensity parity check code LDPC having a code rate R₁, to obtain aninitial bit sequence to be encoded, where 0≤R₂≤R₁≤1; and

the target bit sequence is formed by cascading a first bit sequence anda second bit sequence;

the first bit sequence is obtained by encoding an initial bit sequenceto be encoded with a LDPC having a code rate R₁; and

the second bit sequence is obtained by linearly combining at least twobit sequence segments in the first bit sequence.

The serial numbers of the embodiments of the present disclosure aremerely for description, and do not represent the advantages anddisadvantages of the embodiments.

In the above mentioned embodiments of the present disclosure, thedescriptions of the various embodiments are different, and the partsthat are not described in detail in one embodiment can be referred tothe related descriptions of other embodiments.

In the several embodiments provided by the present application, itshould be understood that the disclosed technical contents may beimplemented in other manners. The device embodiments described above aremerely illustrative. For example, the division of the units is only alogical function division. In actual implementation, there may beanother division manner. For example, a plurality of units or componentsmay be combined or may be integrate into another system, or somefeatures can be ignored or not executed. In addition, the mutualcoupling or direct coupling or communication connection shown ordiscussed may be an indirect coupling or communication connectionthrough some interfaces, units or modules, and may be electrical or inother forms.

The units described as separate components may or may not be physicallyseparated, and the components displayed as units may or may not bephysical units, that is, may be located in one place, or may bedistributed over a plurality network units. Some or all of the units maybe selected according to actual needs to achieve the purpose of thesolution of the embodiment.

In addition, each functional unit in each embodiment of the presentdisclosure may be integrated into one processing unit, or each unit mayexist physically separately, or two or more units may be integrated intoone unit. The above integrated unit can be implemented in the form ofhardware or in the form of a software functional unit.

The integrated units, if implemented in the form of a softwarefunctional unit and sold or used as a standalone product, may be storedin a computer readable storage medium. Based on such understanding, theessence or the part contributing to the prior art of the technicalsolutions of the present disclosure may be embodied in the form of asoftware product stored in a storage medium. A number of instructionsare included to cause a computer device (which may be a personalcomputer, server or network device, etc.) to perform all or part of thesteps of the methods described in various embodiments of the presentdisclosure. The storage medium includes: a U disk, a Read-Only Memory(ROM), a Random Access Memory (RAM), a removable hard disk, a magneticdisk, or an optical disk, and the like.

The above description is only exemplary embodiments of the presentdisclosure, and is not intended to limit the present disclosure, andvarious modifications and changes can be made by those skilled in theart to the present disclosure. Any modifications, equivalentsubstitutions, improvements, etc. made within the spirit and scope ofthe present disclosure are intended to be included within the scope ofthe present disclosure.

INDUSTRIAL APPLICABILITY

In the technical solution provided by the embodiments of the presentdisclosure, the initial bit sequence is encoded with the LDPC of a lowcode rate R₁, to obtain a first bit sequence, and the first bit sequenceis segmented. Then, at least two bit sequence segments in the first bitsequence are combined linearly to obtain a second bit sequence. Thefirst bit sequence and the second bit sequence are cascaded to obtain atarget bit sequence of a lower code rate R₂, where 0≤R₂≤R₁≤1. In thisway, the code rate during the transmission of the target bit sequence isthe relatively low code rate R₂, and this can ensure the propagationspeed. In the decoding stage, since the target bit sequence is obtainedby cascading the first bit sequence and the second bit sequence, thedecoder can directly decode with the LDPC of the code rate R₁.Therefore, the present disclosure can solve the problem in the relatedart that low code rate LDPC encoding will increase the decoding delayand hardware complexity of the decoder, and can thus achieve an effectthat the decoding delay and hardware complexity of the decoder won't beincreased while obtaining a LDPC encoding of a low code rate.

What is claimed is:
 1. An encoding method comprising: encoding aninitial bit sequence to be encoded with a low density parity check codeLDPC having a code rate R₁, to obtain a first bit sequence, where0≤R₁≤1; dividing the first bit sequence into t bit sequence segments,wherein a relationship exists between the number t of the bit sequencesegments and the code rate R₁:${t = \left\lbrack \left\lbrack \frac{j}{R_{1}} \right\rbrack \right\rbrack},$where t is a positive integer greater than or equal to 1, j is apositive integer, and the operator

represents a rounding operation; linearly combining at least two bitsequence segments in the first bit sequence to obtain a second bitsequence, wherein linearly combining at least two bit sequence segmentsin the first bit sequence to obtain a second bit sequence comprises: aselecting step of selecting t₁ bit sequence segments from t bit sequencesegments; a combining step of linearly combining bits at correspondingpositions in the t₁ bit sequence segments to obtain a bit sequencesegment D₁, where 1<t₁≤t; repeating the selecting step and the combiningstep to generate w bit sequence segments {D₁, D₂, . . . , D_(w)}, wherew is a positive integer; and cascading the w bit sequence segments toobtain the second bit sequence; and cascading the first bit sequence andthe second bit sequence to obtain a target bit sequence having a coderate R₂, where 0≤R₂≤R₁≤1.
 2. The method according to claim 1, whereinlinearly combining bits at corresponding positions in the t₁ bitsequence segments comprises at least one of: performing binary additionof bits at corresponding positions in the t₁ bit sequence segments; andfirst performing interleaving on at least two bit sequence segments ofthe t₁ bit sequence segments, and then performing binary addition ofbits at corresponding positions in the t₁ bit sequence segments.
 3. Themethod according to claim 1, wherein selecting t₁ bit sequence segmentsfrom t bit sequence segments comprises at least one of: performingselection according to a pre-determined rule between an encoding end anda decoding end; performing selection according to an indication in asignal sent from the encoding end to the decoding end; and performingselection according to an indication in a signal sent from the decodingend to the encoding end.
 4. The method according to claim 1, wherein thenumber w of bit sequence segments is determined according to t, R₁, andR₂.
 5. The method according to claim 4, wherein the number w of bitsequence segments of the second bit sequence is determined according toa formula of:${w = \left\lbrack \left\lbrack {t \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)} \right\rbrack \right\rbrack},$where, the operator

represents a rounding operation.
 6. The method according to claim 1,wherein a bit length L₂ of the second bit sequence is determinedaccording to L₁, R₁, and R₂, wherein L₁ is a bit length of the first bitsequence.
 7. The method according to claim 6, wherein the bit length L₂of the second bit sequence is determined according to a formula of${L_{2} = \left\lbrack \left\lbrack {L_{1} \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)} \right\rbrack \right\rbrack},$where, the operator

represents a rounding operation.
 8. The method according to claim 1,wherein when R₁=1/3, R₂=1/5, and the first bit sequence comprises 3 bitsequence segments {P1, P2, P3}, the method further comprises: linearlycombining the bit sequence segments P1 and P2, and linearly combiningthe bit sequence segments P1 and P3 to obtain a second bit sequence; andcascading the first bit sequence and the second bit sequence to obtain atarget bit sequence having a code rate R₂=1/5.
 9. A decoding methodcomprising: decoding a target bit sequence having a code rate R₂ with alow density parity check code LDPC having a code rate R₁, to obtain aninitial bit sequence to be encoded, where 0≤R₂≤R₁≤1, wherein the targetbit sequence is formed by cascading a first bit sequence and a secondbit sequence, the first bit sequence is obtained by encoding an initialbit sequence to be encoded with a LDPC having a code rate R₁, and thesecond bit sequence is obtained by dividing the first bit sequence intot bit sequence segments and linearly combining at least two bit sequencesegments in the first bit sequence, wherein a relationship existsbetween the number t of the bit sequence segments and the code rate R₁:${t = \left\lbrack \left\lbrack \frac{j}{R_{1}} \right\rbrack \right\rbrack},$wherein t is a positive integer greater than or equal to 1, j is apositive integer, and the operator

represents a rounding operation; and linearly combining at least two bitsequence segments in the first bit sequence comprises: a selecting stepof selecting t₁ bit sequence segments from t bit sequence segments; acombining step of linearly combining bits at corresponding positions inthe t₁ bit sequence segments to obtain a bit sequence segment D₁, where1<t₁≤t; repeating the selecting step and the combining step to generatew bit sequence segments {D₁, D₂, . . . , D_(w)}, where w is a positiveinteger; and cascading the w bit sequence segments to obtain the secondbit sequence.
 10. An encoding device, comprising: a processor; a memoryfor storing instructions executable by the processor; wherein theprocessor is configured to: encode an initial bit sequence to be encodedwith a low density parity check code LDPC having a code rate R₁, toobtain a first bit sequence, where 0≤R₁≤1; divide the first bit sequenceinto t bit sequence segments, wherein a relationship exists between thenumber t of the bit sequence segments and the code rate R₁:${t = \left\lbrack \left\lbrack \frac{j}{R_{1}} \right\rbrack \right\rbrack},$where t is a positive integer greater than or equal to 1, j is apositive integer, and the operator

represents a rounding operation; linearly combine at least two bitsequence segments in the first bit sequence to obtain a second bitsequence, wherein the processor is further configured to: select t₁ bitsequence segments from t bit sequence segments of the first bitsequence; linearly combine bits at corresponding positions in the t₁ bitsequence segments to obtain a bit sequence segment D₁, where 1<t₁≤t; andcascade w bit sequence segments {D₁, D₂, . . . , D_(w)} generated by theselection unit and the combining unit to obtain the second bit sequence,where w is a positive integer; and cascade the first bit sequence andthe second bit sequence to obtain a target bit sequence having a coderate R₂, where 0≤R₂≤R₁≤1.
 11. The device according to claim 10, whereinthe processor is further configured to perform at least one of:performing binary addition of the bits at corresponding positions in thet₁ bit sequence segments; and first performing interleaving on at leasttwo bit sequence segments of the t₁ bit sequence segments, and thenperforming binary addition of the bits at corresponding positions in thet₁ bit sequence segments.
 12. The device according to claim 10, whereinthe processor is further configured to: according to a pre-determinedrule between an encoding end and a decoding end, select t₁ bit sequencesegments from t bit sequence segments; according to an indication in asignal sent from the encoding end to the decoding end, select t₁ bitsequence segments from t bit sequence segments; and according to anindication in a signal sent from the decoding end to the encoding end,select t₁ bit sequence segments from t bit sequence segments.
 13. Thedevice according to claim 10, wherein the number w of bit sequencesegments of the second bit sequence is determined according to t, R₁,and R₂.
 14. The device according to claim 13, wherein the number w ofbit sequence segments of the second bit sequence is determined accordingto a formula of:${w = \left\lbrack \left\lbrack {t \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)} \right\rbrack \right\rbrack},$where, the operator

represents a rounding operation.
 15. The device according to claim 10,wherein a bit length L₂ of the second bit sequence is determinedaccording to L₁, R₁, and R₂, wherein L₁ is a bit length of the first bitsequence.
 16. The device according to claim 15, wherein the bit lengthL₂ of the second bit sequence is determined according to a formula of:${L_{2} = \left\lbrack \left\lbrack {L_{1} \cdot \left( {\frac{R_{1}}{R_{2}} - 1} \right)} \right\rbrack \right\rbrack},$where, the operator

represents a rounding operation.